1. Field of the Invention
The present invention relates to a low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process, that is, a process without short-circuited double polysilicon.
2. Description of the Related Art
In the present advanced process for manufacturing EEPROM memory devices it is quite difficult to obtain a good contact structure for a select transistor due to the high resistivity of the polysilicon layers constituting the transistor gates.
This difficulty is particularly present in the processes that do not provide short circuited double polysilicon (NO-DPCC) where the contact structure of the select transistor is obtained by means of complex process steps and expensive additional masks.
With reference to FIG. 1, a plan view of the geometrical structure of a conventional EEPROM memory cell is shown. The single memory cell is constituted by a select transistor 1, typical of nonvolatile EEPROM memories, connected in series to a storing transistor 2 wherein it can be noted a floating gate 3 (lower polysilicon) where the electrical charges are stored, a control gate 4 (upper polysilicon), a tunnel oxide area 5 (with a thickness of about 80 xc3x85) through which the electrical charges pass, for Fowler-Nordheim effect, during the programming step. Moreover, there is an area wherein an implant 7 is obtained (usually using phosphorous as dopant) with the purpose of keeping an electrical continuity between the select transistor 1 and the tunnel area 5. The memory cell further includes drain regions 8a and source regions 8b, and an upper polysilicon layer 6 of the select transistor 1, which forms a word line of the memory matrix.
FIG. 2 shows a section view along line IIxe2x80x94II of FIG. 1. It can be noted the superimposed layers structure both of the select transistor 1 and of the storing transistor 2.
The select transistor provides a gate oxide layer 11 over a silicon substrate 14, a lower polysilicon layer 10 and the upper polysilicon layer 6 superimposed to it. An intermediate dielectric layer 9 is provided between the two layers. Moreover, the dielectric layer 9 is present between the two polysilicon layers 3 and 4 of the storing transistor, the dielectric layer 9 may be formed by oxide-nitride-oxide (ONO), and has the purpose to electrically insulate the two layers.
The select transistor 1 has the same structure of the storing transistor 2, that is, lower polysilicon/intermediate dielectric/upper polysilicon, in order to preserve a planarity over the entire matrix.
Oxide spacers 12 are present at the sidewalls of the two transistors 1 and 2.
Provided between the two transistors, and connected in series with them, is a doped region 13 formed in the silicon substrate 14. The doped region 13 is equivalent to a source region for the select transistor 1 and to a drain region for the storing memory 2. The doped region 13 is electrically connected to the implant region 7 to keep an electrical connection between the select transistor 1 and the tunnel area 5.
FIG. 3 shows a section view along line IIIxe2x80x94III of FIG. 1. It should be noted that the select transistor 1 includes the two polysilicon layers 6 and 10, which are electrically insulated by the intermediate dielectric 9, even on field oxide regions 15 (LOCOS), as typically provided by a NO-DPCC process.
In a process providing short-circuited double polysilicon (DPCC not shown), the lower polysilicon and the upper polysilicon are short-circuited on the field oxide, using an appropriate mask, in order to make it possible to bias the select transistor gate by means of a contact on the upper polysilicon. Typically, this occurs every 8 memory cells (1 byte).
In a NO-DPCC process, there are problems related to defining a contact to the select transistor. FIG. 4 shows a section view, along a memory matrix row, of a select transistor obtained by means of a NO-DPCC process. A contact on the oxide field is present. The select transistor structure is analogous to that of FIG. 3, with the addition of an upper dielectric layer 16 formed over the entire device with the purpose of electrically insulating the polysilicon layers from possible superimposed metal layers. A contact element 17 (for example, formed from tungsten) is informed in the upper dielectric layer 16 over the field oxide 15, and has the purpose of connecting the lower polysilicon layer 10 with a metal line 18 in order to activate the select transistor gate.
The contact element 17 is connected to the lower polysilicon layer 10 rather than to the upper layer 6, as is typical in a DPCC process, because the two polysilicon layers are electrically insulated as a result of being manufactured by means of a NO-DPCC process.
However, there are problems related to such a contact structure. For example, unlike a DPCC process, no short-circuiting between the lower polysilicon 10 and the upper polysilicon 6 is provided, and so it is necessary to introduce one or more masks for directly contacting the lower polysilicon 10 of the select transistor 1. Additionally, the lower polysilicon 10 typically has a high resistance which result in problems with delay in the electrical signal propagation. Furthermore, the thickness of the lower polysilicon layer 10 is typically less than that of the upper polysilicon layer 6. Consequently, the process steps for defining polysilicon contacts can cause problems of breaking down the lower polysilicon 10.
As a result, in a NO-DPCC process that does not provide short-circuited double polysilicon, the manufacture of a contact structure for the select transistor becomes a very critical step.
In view of the state of the art described, it is an object of the embodiments of the present invention to provide a low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process.
According to embodiments of the present invention, such object is achieved by means of a semiconductor memory device, including at least one memory cell row. Each memory cell includes an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer, and an upper polysilicon layer superimposed to said gate oxide region and electrically insulated therebetween by an intermediate dielectric layer interposed between them. The gate oxide regions of the select transistors are separated by field oxide regions. The lower and upper polysilicon layers, and the intermediate dielectric layer, extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row is at least one opening in the upper polysilicon layer, the intermediate dielectric layer, and the lower polysilicon layer. A first contact element suitable to electrically connect said lower and upper polysilicon layers is inserted inside the opening.
The features and advantages of embodiments of the present invention will be made more evident by the following detailed description of a particular embodiment thereof, illustrated as a non-limiting example in the accompanying drawings.